A semiconductor device including an array of memory cells may include memory cells located at an intersection between conductive access lines, such as between a conductive word line and a conductive bit line. For example, three-dimensional (3D) cross-point memory devices may include a plurality of memory cells arranged in an array and including a plurality of rows of access lines and a plurality of columns of access lines that may be arranged in a pattern of rows and columns. During operation of the semiconductor device, data may be written to and read from the memory cells. A particular memory cell may be accessed through the conductive access lines in direct electrical communication with that particular memory cell.
As the demand for higher-density memory cell arrays increases, the size of individual cells in a memory array may shrink, the memory array may include more memory cells, or both. As the number of memory cells in the array increases, the number of memory cells in electrical communication with each access line (e.g., with each conductive word line and each conductive bit line) increases. However, as the number of memory cells in electrical communication with the access lines increases, the capacitance of the access lines used to access a particular memory cell is increased.
When an access line is charged during programming (e.g., during a write operation) and/or a read operation, an electric charge may accumulate on the access line. The electric charge may be proportional to the number of memory cells along the entire access line. After the memory cell is selected, the semiconductor device may exhibit a so-called “snapback” effect, in which a voltage across the selected memory cell is rapidly reduced. The snapback effect may be accompanied by a discharge current flowing through the accessed memory cell. However, if the discharge current is too high, the memory cell may be damaged and the performance of the semiconductor device may be negatively impacted. By way of nonlimiting example, too high a discharge current through the memory cell may disturb a programmed state of the selected memory cell for a read operation, may change a threshold voltage during cycling of the memory cells associated with the semiconductor device, and may cause a threshold voltage of different memory cells in the array to be different.